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LT1725 General Purpose Isolated Flyback Controller
FEATURES
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DESCRIPTIO
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Drives External Power MOSFET with External ISENSE Resistor Application Input Voltage Limited Only by External Power Components Senses Output Voltage Directly from Primary Side Winding--No Optoisolator Required Accurate Regulation Without User Trims Regulation Maintained Well into Discontinuous Mode Switching Frequency from 50kHz to 250kHz with External Capacitor Optional Load Compensation Optional Undervoltage Lockout Available in 16-Pin SO and SSOP Packages
The LT(R)1725 is a monolithic switching regulator controller specifically designed for the isolated flyback topology. It drives the gate of an external MOSFET and is generally powered from a third transformer winding. These features allow for an application input voltage limited only by external power path components. The third transformer winding also provides output voltage feedback information, such that an optoisolator is not required. Its gate drive capability coupled with a suitable external MOSFET can deliver load power up to tens of watts. The LT1725 has a number of features not found on most other switching regulator ICs. By utilizing current mode switching techniques, it provides excellent AC and DC line regulation. Its unique control circuitry can maintain regulation well into discontinuous mode in most applications. Optional load compensation circuitry allows for improved load regulation. An optional undervoltage lockout pin halts operation when the application input voltage is too low. An optional external capacitor implements a softstart function. A 3V output is available at up to several mA for powering primary side application circuitry.
APPLICATIO S
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Telecom Isolated Converters Offline Isolated Power Supplies Instrumentation Power Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
48V to Isolated 5V Converter
CTX02-14989 6 LT1725 35.7k 1% 3VOUT FB 3.01k 1% 1nF 47pF SFST VC OSCAP 820k 51k 51k MENAB 51k 2.7k ROCMP RCMPC 0.1F SGND GATE ISENSE PGND 0.18
1725 TA01a
BAS16 22
VIN 36V TO 72V 1
18
470pF
47k VCC
15F
1F
12CWQ06
VOUT (V)
+
68 150pF 1.5F
2
9
VOUT = 5V IOUT = 0 to 2A 51 1W
11 10
tON ENDLY
UVLO 100pF 33k
+
150F
4.75 0 0.5 1.0 ILOAD (A) 1.5 2.0
1725 F10b
4
12 IRF620
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Output Load Regulation
5.25 VIN = 48V VIN = 36V VIN = 72V 5.00
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LT1725
ABSOLUTE
(Note 1)
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RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW PGND 1 ISENSE 2 SFST 3 ROCMP 4 RCMPC 5 OSCAP 6 VC 7 FB 8 16 GATE 15 VCC 14 tON 13 ENDLY 12 MINENAB 11 SGND 10 UVLO 9 3VOUT
VCC Supply Voltage ................................................. 22V UVLO Pin Voltage .................................................... VCC ISENSE Pin Voltage .................................................... 2V FB Pin Current ..................................................... 2mA Operating Junction Temperature Range LT1725C .............................................. 0C to 100C LT1725I ........................................... -40C TO 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................ 300C
ORDER PART NUMBER LT1725CGN LT1725CS LT1725IGN LT1725IS GN PART MARKING 1725 1725I
GN PACKAGE S PACKAGE 16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO
TJMAX = 125C, JA = 110C/W (GN) TJMAX = 125C, JA = 100C/W (SO)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL Power Supply VCC VCC Turn-On Voltage VCC Turn-Off Voltage VCC Hysteresis (Note 3) Supply Current Start-Up Current Feedback Voltage PARAMETER
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
CONDITIONS
q q q q q
MIN 14.0 8 4.0 6
TYP 15.1 9.7 5.4 10 120 1.245 500
MAX 16.0 11 6.5 15 280 1.260 1.270 1800 80 0.05 50
UNITS V V V mA A V V nA mho A V %/V V/V A mA V V
(VTURN-ON - VTURN-OFF) VC = Open
ICC
Feedback Amplifier VFB IFB gm ISRC, ISNK VCL
q
1.230 1.220 400 30
Feedback Pin Input Current Feedback Amplifier Transconductance Feedback Amplifier Source or Sink Current Feedback Amplifier Clamp Voltage Reference Voltage/Current Line Regulation Voltage Gain Soft-Start Charging Current Soft-Start Discharge Current 12V VIN 18V VC = 1V to 2V VSFST = 0V VSFST = 1.5V, VUVLO = 0V IGATE = 100mA IGATE = 500mA IGATE = 100mA IGATE = 500mA VGATE = 2V CL = 1000pF CL = 1000pF
q q q q q q
lC = 10A
q q
1000 50 2.5 0.01 2000
25 0.8 11.5 11.0
40 1.5 12.1 11.8 0.3 0.6
Gate Output VGATE Output High Level Output Low Level IGATE tr tf Output Sink Current in Shutdown, VUVLO = 0V Rise Time Fall Time
0.45 1.0
1.2
2.5 30 30
2
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V V mA ns ns
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LT1725
ELECTRICAL CHARACTERISTICS
SYMBOL VC VISENSE PARAMETER Control Pin Threshold Switch Current Limit Current Amplifier Duty Cycle = Min
q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
CONDITIONS MIN 0.90 0.80 220 200 TYP 1.12 250 220 0.30 COSCAP = 100pF
q
MAX 1.25 1.35 270 280
UNITS V V mV mV mV mV
Duty Cycle 30% Duty Cycle 30% Duty Cycle = 80%
q
VISENSE/VC Timing f COSCAP tON tED tEN Rt Switching Frequency Oscillator Capacitor Value Minimum Switch On Time Flyback Enable Delay Time Minimum Flyback Enable Time Timing Resistor Value Maximum Switch Duty Cycle Load Compensation Sense Offset Voltage Current Gain Factor UVLO Function VUVLO IUVLO UVLO Pin Threshold UVLO Pin Bias Current VUVLO = 1.2V VUVLO = 1.3V ILOAD = 1mA
q q
90 80 33
100
115 125 200
kHz kHz pF ns ns ns
(Note 2) RtON = 50k RENDLY = 50k RMENAB = 50k (Note 2)
q
200 200 200 24 85 90 2 0.80 1.21 - 0.25 - 4.50 2.8 8 0.95 1.25 + 0.1 - 3.5 3.0 10
q
200
k %
5 1.05 1.29 + 0.25 - 2.50 3.2
mV mV V A A V mA
3V Output Function VREF Reference Output Voltage Output Impedance Current Limit Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Component value range guaranteed by design. Note 3: The VCC turn-on/turn-off voltages and hysteresis voltage are proportional in magnitude to each other-guaranteed by design.
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LT1725 TYPICAL PERFOR A CE CHARACTERISTICS
VCC Turn-On Voltage vs Temperature
16.00
VCC HYSTERESIS VOLTAGE (V)
15.75
VCC TURN-ON VOLTAGE (V)
15.50 15.25 15.00 14.75 14.50 14.25 -50 -25
6.00 5.75 5.50 5.25 5.00 4.75 -50 -25
START-UP CURRENT (A)
50 25 75 0 TEMPERATURE (C)
Supply Current vs Temperature
13 UVLO PIN INPUT CURRENT (A)
1
12 SUPPLY CURRENT (mA)
-1 -2 -3 -4 -5 -6 -50 -25 VUVLO = 1.3V
OSCILLATOR FREQUENCY (kHz)
11
10
9
8 -50 -25
50 25 0 75 TEMPERATURE (C)
VC CLAMP VOLTAGE, SWITCHING THRESHOLD (V)
VGATE vs ISINK
1.0
0.8 TA = 125C
VGATE (V)
0.6 TA = 25C 0.4
VCC-VGATE (V)
0.2
TA = -55C
0 1 10 ISINK (mA)
1725 G07
100
4
UW
100
1725 G01
VCC Hysteresis Voltage vs Temperature
6.50 6.25 250
Start-Up Current vs Temperature
200
150
100
50
125
50 25 75 0 TEMPERATURE (C)
100
125
0 -50
-25
50 0 75 25 TEMPERATURE (C)
100
125
1725 G02
1725 G03
UVLO Pin Input Current vs Temperature
115
VUVLO = 1.2V
Oscillator Frequency vs Temperature
0
110 105 100 95 90 85 -50 -25
100
125
50 25 75 0 TEMPERATURE (C)
100
125
50 25 75 0 TEMPERATURE (C)
100
125
1725 G04
1725 G05
1725 G06
VCC-VGATE vs ISOURCE
0 -0.5 -1.0 TA = 125C TA = 25C -1.5 -2.0 -2.5 -3.0
1000 3.0 2.5 2.0 1.5 1.0 0.5
VC Clamp Voltage, Switching Threshold vs Temperature
CLAMP VOLTAGE
TA = -55C
SWITCHING THRESHOLD
1
10 100 ISOURCE (mA)
1000
1725 G08
0 -50
-25
50 25 75 0 TEMPERATURE (C)
100
125
1725 G09
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LT1725 TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Switch-On Time vs Temperature
275
MINIMUM SWITCH-ON TIME (ns)
RTON = 50k
MINIMUM ENABLE TIME (ns)
250 225 200 175 150 125 -50
ENABLE DELAY TIME (ns)
-25
50 25 75 0 TEMPERATURE (C)
FEEDBACK AMPLIFIER TRANSCONDUCTANCE (mho)
Feedback Amplifier Output Current vs FB Pin Voltage
FEEDBACK AMPLIFIER OUTPUT CURRENT (A)
80 60 40 20 0 -20 TA = 125C -40 -60 -80 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 FB PIN VOLTAGE (V)
1725 G13
TA = 25C
Soft-Start Charging Current vs Temperature
60
SOFT-START CHARGING CURRENT (A)
50 40 30 20 10 0 -50
SOFT-START SINK CURRENT (mA)
-25
UW
100
1725 G10
Minimum Enable Time vs Temperature
275 250 225 200 175 150 125 -50 RMINENAB = 50k
Enable Delay Time vs Temperature
275 250 225 200 175 150 125 -50
125
-25
50 25 75 0 TEMPERATURE (C)
100
125
-25
50 25 75 0 TEMPERATURE (C)
100
125
1725 G11
1725 G12
Feedback Amplifier Transconductance vs Temperature
1600 1400 1200 1000 800 600 400 200 -50 -25
TA = -55C
50 25 75 0 TEMPERATURE (C)
100
125
1725 G14
Soft-Start Sink Current vs Temperature
2.5 V(SFST) = 1.5V 2.0
V(SFST) = 0V
1.5
1.0
0.5
50 25 75 0 TEMPERATURE (C)
100
125
0 -50
-25
50 0 75 25 TEMPERATURE (C)
100
125
1725 G15
1725 G16
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LT1725
PI FU CTIO S
PGND (Pin 1): The power ground pin carries the GATE node discharge current. This is typically a current spike of several hundred mA with a duration of tens of nanoseconds. It should be connected directly to a good quality ground plane. ISENSE (Pin 2): Pin to measure switch current with external sense resistor. The sense resistor should be of a noninductive construction as high speed performance is essential. Proper grounding technique is also required to avoid distortion of the high speed current waveform. A preset internal limit of nominally 250mV at this pin effects a switch current limit. SFST (Pin 3): Pin for optional external capacitor to effect soft-start function. See Applications Information for details. ROCMP (Pin 4): Input pin for optional external load compensation resistor. Use of this pin allows nominal compensation for nonzero output impedance in the power transformer secondary circuit, including secondary winding impedance, output Schottky diode impedance and output capacitor ESR. In less demanding applications, this resistor is not needed. See Applications Information for more details. RCMPC (Pin 5): Pin for external filter capacitor for optional load compensation function. A common 0.1F ceramic capacitor will suffice for most applications. See Applications Information for further details. OSCAP (Pin 6): Pin for external timing capacitor to set oscillator switching frequency. See Applications Information for details. VC (pin 7): This is the control voltage pin which is the output of the feedback amplifier and the input of the current comparator. Frequency compensation of the overall loop is effected in most cases by placing a capacitor between this node and ground. FB (Pin 8): Input pin for external "feedback" resistor divider. The ratio of this divider, times the internal bandgap (VBG) reference, times the effective output-tothird winding transformer turns ratio is the primary determinant of the output voltage. The Thevenin equivalent resistance of the feedback divider should be roughly 3k. See Applications Information for more details. 3VOUT (Pin 9): Output pin for nominal 3V reference. This facilitates various user applications. This node is internally current limited for protection and is intended to drive either moderate capacitive loads of several hundred pF or less, or, very large capacitive loads of 0.1F or more. See Applications Information for more details. UVLO (Pin 10): This pin allows the use of an optional external resistor divider to set an undervoltage lockout based upon VIN (not VCC) level. (Note: If the VCC voltage is sufficient to allow the part to start up, but the UVLO pin is held below its threshold, output switching action will be disabled, but the part will draw its normal quiescent current from VCC. This typically causes a benign relaxation oscillation action on the VCC pin in the conventional "trickle-charge" bootstrapped configuration.) The bias current on this pin is a function of the state of the UVLO comparator; as the threshold is exceeded, the bias current increases. This creates a hysteresis band equal to the change in bias current times the Thevenin impedance of the user's resistive divider. The user may thereby adjust the impedance of the UVLO divider to achieve a desired degree of hysteresis. A 100pF capacitor to ground is recommended on this pin. See Applications Information for details. SGND (Pin 11): The signal ground pin is a clean ground. The internal reference, oscillator and feedback amplifier are referred to it. Keep the ground path connection to the FB pin, OSCAP capacitor and the VC compensation capacitor free of large ground currents. MINENAB (Pin 12): Pin for external programming resistor to set minimum enable time. See Applications Information for details.
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LT1725
PI FU CTIO S
ENDLY (Pin 13): Pin for external programming resistor to set enable delay time. See Applications Information for details. tON (Pin 14): Pin for external programming resistor to set switch minimum on time. See Applications Information for details. VCC (Pin 15): Supply voltage for the LT1725. Bypass this pin to ground with 1F or more. GATE (Pin 16): This is the gate drive to the external power MOSFET switch and has large dynamic currents flowing through it. Keep the trace to the MOSFET as short as possible to minimize electromagnetic radiation and voltage spikes. A series resistance of 5 or more may help to dampen ringing in less than ideal layouts.
BLOCK DIAGRA
UVLO BIAS
OSCAP OSC LOGIC MOSFET DRIVER
FB FDBK SOFT-START LOAD COMPENSATION
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VCC
3VOUT
3V REG (INTERNAL) tON MINENAB ENDLY
GATE
PGND
ISENSE COMP IAMP SGND
1725 BD
VC
SFST
ROCMP
RCMPC
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LT1725 TI I G DIAGRA W
COLLAPSE DETECT VFLBK 0.80x VFLBK ON ENABLE DELAY DISABLED MINIMUM ENABLE TIME ENABLED DISABLED
1725 TD
FLYBACK ERROR A PLIFIER
T1 D1
R1
R2 I IM
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8
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UW
VSW VOLTAGE
VIN
GND SWITCH STATE OFF OFF ON
MINIMUM tON FLYBACK AMP STATE
*
+ +
C1 ISOLATED VOUT
VIN
* *
-
M1 IM IFXD VC FB Q1 Q2 VBG C2 ENAB
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OPERATIO
The LT1725 is a current mode switcher controller IC designed specifically for the isolated flyback topology. The Block Diagram shows an overall view of the system. Many of the blocks are similar to those found in traditional designs, including: Internal Bias Regulator, Oscillator, Logic, Current Amplifier and Comparator, Driver and Output Switch. The novel sections include a special Flyback Error Amplifier and a Load Compensation mechanism. Also, due to the special dynamic requirements of flyback control, the Logic system contains additional functionality not found in conventional designs. The LT1725 operates much the same as traditional current mode switchers, the major difference being a different type of error amplifier that derives its feedback information from the flyback pulse. Due to space constraints, this discussion will not reiterate the basics of current mode switcher/controllers and isolated flyback converters. A good source of information on these topics is Application Note AN19. ERROR AMPLIFIER--PSEUDO DC THEORY Please refer to the simplified diagram of the Flyback Error Amplifier. Operation is as follows: when MOSFET output switch M1 turns off, its drain voltage rises above the VIN rail. The amplitude of this flyback pulse as seen on the third winding is given as:
VFLBK =
( VOUT + VF + ISEC * ESR)
NST
VF = D1 forward voltage ISEC = transformer secondary current ESR = total impedance of secondary circuit NST = transformer effective secondary-to-third winding turns ratio The flyback voltage is then scaled by external resistor divider R1/R2 and presented at the FB pin. This is then compared to the internal bandgap reference by the differential transistor pair Q1/Q2. The collector current from Q1 is mirrored around and subtracted from fixed current source IFXD at the VC pin. An external capacitor integrates this net current to provide the control voltage to set the current mode trip point.
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The relatively high gain in the overall loop will then cause the voltage at the FB pin to be nearly equal to the bandgap reference VBG. The relationship between VFLBK and VBG may then be expressed as:
VFLBK =
(R1+ R2) V
R2
BG
Combination with the previous VFLBK expression yields an expression for VOUT in terms of the internal reference, programming resistors, transformer turns ratio and diode forward voltage drop:
VOUT = VBG
(R1+ R2)
R2
1 - VF - ISEC * ESR NST
Additionally, it includes the effect of nonzero secondary output impedance, which is discussed below in further detail, see Load Compensation Theory. The practical aspects of applying this equation for VOUT are found in the Applications Information section. So far, this has been a pseudo-DC treatment of flyback error amplifier operation. But the flyback signal is a pulse, not a DC level. Provision must be made to enable the flyback amplifier only when the flyback pulse is present. This is accomplished by the dotted line connections to the block labeled "ENAB". Timing signals are then required to enable and disable the flyback amplifier. ERROR AMPLIFIER--DYNAMIC THEORY There are several timing signals which are required for proper LT1725 operation. Please refer to the Timing Diagram. Minimum Output Switch On Time The LT1725 effects output voltage regulation via flyback pulse action. If the output switch is not turned on at all, there will be no flyback pulse and output voltage information is no longer available. This would cause irregular loop response and start-up/latchup problems. The solution chosen is to require the output switch to be on for an absolute minimum time per each oscillator cycle. This in turn establishes a minimum load requirement to maintain regulation. See Applications Information for further details.
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LT1725
OPERATIO
Enable Delay
When the output switch shuts off, the flyback pulse appears. However, it takes a finite time until the transformer primary side voltage waveform approximately represents the output voltage. This is partly due to rise time on the MOSFET drain node, but more importantly, due to transformer leakage inductance. The latter causes a voltage spike on the primary side not directly related to output voltage. (Some time is also required for internal settling of the feedback amplifier circuitry.) In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turnoff command and the enabling of the feedback amplifier. This is termed "enable delay". In certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. See Applications Information for further details. Collapse Detect Once the feedback amplifier is enabled, some mechanism is then required to disable it. This is accomplished by a collapse detect comparator, which compares the flyback voltage (FB referred) to a fixed reference, nominally 80% of VBG. When the flyback waveform drops below this level, the feedback amplifier is disabled. This action accommodates both continuous and discontinuous mode operation.
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Minimum Enable Time The feedback amplifier, once enabled, stays enabled for a fixed minimum time period termed "minimum enable time." This prevents lockup, especially when the output voltage is abnormally low, e.g., during start-up. The minimum enable time period ensures that the VC node is able to "pump up" and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. The "minimum enable time" often determines the low load level at which output voltage regulation is lost. See Applications Information for details. Effects of Variable Enable Period It should now be clear that the flyback amplifier is enabled during only a portion of the cycle time. This can vary from the fixed "minimum enable time" described to a maximum of roughly the "off" switch time minus the enable delay time. Certain parameters of flyback amp behavior will then be directly affected by the variable enable period. These include effective transconductance and VC node slew rate. LOAD COMPENSATION THEORY The LT1725 uses the flyback pulse to obtain information about the isolated output voltage. A potential error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier,
T1 VIN IM R1 M1 FB Q1 Q2 R2 LOAD COMP I VBG Q3 A1
+ -
R3 50k ISENSE
IM
ROCMP
RCMPC
RSENSE
1725 F01
Figure 1. Load Compensation Diagram
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LT1725
OPERATIO
transformer secondary and output capacitor. This has been represented previously by the expression "ISEC * ESR." However, it is generally more useful to convert this expression to an effective output impedance. Because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the OFF duty cycle. That is:
1 ROUT = ESR where DCOFF
ROUT = effective supply output impedance ESR = lumped secondary impedance DCOFF = OFF duty cycle Expressing this in terms of the ON duty cycle, remembering DCOFF = 1 - DC,
1 ROUT = ESR 1- DC
DC = ON duty cycle In less critical applications, or if output load current remains relatively constant, this output impedance error may be judged acceptable and the external FB resistor divider adjusted to compensate for nominal expected error. In more demanding applications, output impedance error may be minimized by the use of the load compensation function. To implement the load compensation function, a voltage is developed that is proportional to average output switch current. This voltage is then impressed across the external ROCMP resistor, and the resulting current acts to increase the VBG reference used by the flyback error amplifier. As output loading increases, average switch current increases to maintain rough output voltage regulation. This causes an increase in ROCMP resistor current which effects a corresponding increase in target output voltage. Assuming a relatively fixed power supply efficiency, Eff, Power Out = Eff * Power In VOUT * IOUT = Eff * VIN * IIN Average primary side current may be expressed in terms of output current as follows:
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V IIN = OUT * IOUT VIN * EFF
combining the efficiency and voltage terms in a single variable: IIN = K1 * IOUT, where
V K1= OUT VIN * EFF
Switch current is converted to voltage by the external sense resistor and averaged/lowpass filtered by R3 and the external capacitor on RCMPC. This voltage is then impressed across the external ROCMP resistor by op amp A1 and transistor Q3. This produces a current at the collector of Q3 which is then mirrored around and then subtracted from the FB node. This action effectively increases the voltage required at the top of the R1/R2 feedback divider to achieve equilibrium. So the effective change in VOUT target is:
R VOUT = K1 * IOUT SENSE * (R1|| R2) or ROCMP R VOUT = K1 SENSE * (R1|| R2) IOUT ROCMP
(
)
Nominal output impedance cancellation is obtained by equating this expression with ROUT:
R ROUT = K1 SENSE * (R1|| R2) and ROCMP R ROCMP = K1 SENSE * (R1|| R2) where ROUT
K1 = dimensionless variable related to VIN, VOUT and efficiency as above RSENSE = external sense resistor ROUT = uncompensated output impedance (R1||R2) = impedance of R1 and R2 in parallel The practical aspects of applying this equation to determine an appropriate value for the ROCMP resistor are found in the Applications Information section.
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LT1725
APPLICATIO S I FOR ATIO
TRANSFORMER DESIGN CONSIDERATIONS Transformer specification and design is perhaps the most critical part of applying the LT1725 successfully. In addition to the usual list of caveats dealing with high frequency isolated power supply transformer design, the following information should prove useful. Turns Ratios Note that due to the use of the external feedback resistor divider ratio to set output voltage, the user has relative freedom in selecting transformer turns ratio to suit a given application. In other words, "screwball" turns ratios like "1.736:1.0" can scrupulously be avoided! In contrast, simpler ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which yield more freedom in setting total turns and mutual inductance. Turns ratio can then be chosen on the basis of desired duty cycle. However, remember that the input supply voltage plus the secondary-to-primary referred version of the flyback pulse (including leakage spike) must not exceed the allowed external MOSFET breakdown rating. Leakage Inductance Transformer leakage inductance (on either the primary or secondary) causes a spike after output switch turnoff. This is increasingly prominent at higher load currents, where more stored energy must be dissipated. In many cases a "snubber" circuit will be required to avoid overvoltage breakdown at the output switch node. Application Note AN19 is a good reference on snubber design. In situations where the flyback pulse extends beyond the enable delay time, the output voltage regulation will be affected to some degree. It is important to realize that the feedback system has a deliberately limited input range, roughly 50mV referred to the FB node, and this works to the user's advantage in rejecting large, i.e., higher voltage, leakage spikes. In other words, once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. So the user is generally advised to arrange the snubber circuit to clamp at as high a voltage as comfortably possible, observing MOSFET breakdown, such that leakage spike duration is as short as possible.
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As a rough guide, total leakage inductances of several percent (of mutual inductance) or less may require a snubber, but exhibit little to no regulation error due to leakage spike behavior. Inductances from several percent up to perhaps ten percent cause increasing regulation error. Severe leakage inductances in the double digit percentage range should be avoided if at all possible as there is a potential for abrupt loss of control at high load current. This curious condition potentially occurs when the leakage spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback signal! It then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. This will typically reduce the output voltage abruptly to a fraction, perhaps between one-third to two-thirds of its correct value. If load current is reduced sufficiently, the system will snap back to normal operation. When using transformers with considerable leakage inductance, it is important to exercise this worst-case check for potential bistability: 1. Operate the prototype supply at maximum expected load current. 2. Temporarily short circuit the output. 3. Observe that normal operation is restored. If the output voltage is found to hang up at a abnormally low value, the system has a problem. This will usually be evident by simultaneously monitoring the VSW waveform on an oscilloscope to observe leakage spike behavior firsthand. A final note--the susceptibility of the system to bistable behavior is somewhat a function of the load I/V characteristics. A load with resistive, i.e., I = V/R behavior is the most susceptible to bistability. Loads which exhibit "CMOSsy", i.e., I = V2 /R behavior are less susceptible. Secondary Leakage Inductance In addition to the previously described effects of leakage inductance in general, leakage inductance on the secondary in particular exhibits an additional phenomenon. It forms an inductive divider on the transformer secondary,
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LT1725
APPLICATIO S I FOR ATIO
which reduces the size of the primary-referred flyback pulse used for feedback. This will increase the output voltage target by a similar percentage. Note that unlike leakage spike behavior, this phenomena is load independent. To the extent that the secondary leakage inductance is a constant percentage of mutual inductance (over manufacturing variations), this can be accommodated by adjusting the feedback resistor divider ratio. Winding Resistance Effects Resistance in either the primary or secondary will act to reduce overall efficiency (POUT/PIN). Resistance in the secondary increases effective output impedance which degrades load regulation, (at least before load compensation is employed). Bifilar Winding A bifilar or similar winding technique is a good way to minimize troublesome leakage inductances. However remember that this will increase primary-to-secondary capacitance and limit the primary-to-secondary breakdown voltage, so bifilar winding is not always practical. Finally, the LTC Applications group is available to assist in the choice and/or design of the transformer. Happy Winding! SELECTING FEEDBACK RESISTOR DIVIDER VALUES The expression for VOUT developed in the Operation section can be rearranged to yield the following expression for the R1/R2 ratio:
(R1+ R2) = ( VOUT + VF + ISEC * ESR) N
R2 VBG
ST
where: VOUT = desired output voltage VF = switching diode forward voltage ISEC * ESR = secondary resistive losses VBG = data sheet reference voltage value NST = effective secondary-to-third winding turns ratio
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The above equation defines only the ratio of R1 to R2, not their individual values. However, a "second equation for two unknowns" is obtained from noting that the Thevenin impedance of the resistor divider should be roughly 3k for bias current cancellation and other reasons. SELECTING ROCMP RESISTOR VALUE The Operation section previously derived the following expressions for ROUT, i.e., effective output impedance and ROCMP, the external resistor value required for its nominal compensation:
1 ROUT = ESR 1 - DC R ROCMP = K1 SENSE R1|| R2 ROUT
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(
)
While the value for ROCMP may therefore be theoretically determined, it is usually better in practice to employ empirical methods. This is because several of the required input variables are difficult to estimate precisely. For instance, the ESR term above includes that of the transformer secondary, but its effective ESR value depends on high frequency behavior, not simply DC winding resistance. Similarly, K1 appears to be a simple ratio of VIN to VOUT times (differential) efficiency, but theoretically estimating efficiency is not a simple calculation. The suggested empirical method is as follows: Build a prototype of the desired supply using the eventual secondary components. Temporarily ground the RCMPC pin to disable the load compensation function. Operate the supply over the expected range of output current loading while measuring the output voltage deviation. Approximate this variation as a single value of ROUT (straight line approximation). Calculate a value for the K1 constant based on VIN, VOUT and the measured (differential) efficiency. These are then combined with RSENSE as indicated to yield a value for ROCMP. Verify this result by connecting a resistor of roughly this value from the ROCMP pin to ground. (Disconnect the ground short to RCMPC and connect the requisite 0.1F filter capacitor to ground.) Measure the output impedance
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LT1725
APPLICATIO S I FOR ATIO
with the new compensation in place. Modify the original ROCMP value if necessary to increase or decrease the effective compensation. SELECTING OSCILLATOR CAPACITOR VALUE The switching frequency of the LT1725 is set by an external capacitor connected between the OSCAP pin and ground. Recommended values are between 200pF and 33pF, yielding switching frequencies between 50kHz and 250kHz. Figure 2 shows the nominal relationship between external capacitance and switching frequency. To minimize stray capacitance and potential noise pickup, this capacitor should be placed as close as possible to the IC and the OSCAP node length/area minimized.
300
TIME (ns)
100 20 RT (k)
1725 F03
200
fOSC (kHz)
100
50 30
100 COSCAP (pF)
200
1725 F02
Figure 2. fOSC vs OSCAP Value
SELECTING TIMING RESISTOR VALUES There are three internal "one-shot" times that are programmed by external application resistors: minimum on time, enable delay time and minimum enable time. These are all part of the isolated flyback control technique, and their functions have been previously outlined in the Theory of Operation section. Figures 3 shows nominal observed time versus external resistor value for these functions. The following information should help in selecting and/or optimizing these timing values.
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1000 500 100 250
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Figure 3. "One Shot" Times vs Programming Resistor
Minimum On Time This time defines a period whereby the normal switch current limit is ignored. This feature provides immunity to the leading edge current spike often seen at the source node of the external power MOSFET, due to rapid charging of its gate/source capacitance. This current spike is not indicative of actual current level in the transformer primary, and may cause irregular current mode switching action, especially at light load. However, the user must remember that the LT1725 does not "skip cycles" at light loads. Therefore, minimum on time will set a limit on minimum delivered power and consequently a minimum load requirement to maintain regulation (see Minimum Load Considerations). Similarly, minimum on time has a direct effect on short-circuit behavior (see Maximum Load/Short-Circuit Considerations). The user is normally tempted to set the minimum on time to be short to minimize these load related consequences. (After all, a smaller minimum on time approaches the ideal case of zero, or no minimum.) However, a longer time may be required in certain applications based on MOSFET switching current spike considerations. Enable Delay Time This function provides a programmed delay between turnoff of the gate drive node and the subsequent enabling of the feedback amplifier. At high loads, a primary side voltage spike after MOSFET turnoff may be observed due
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LT1725
APPLICATIO S I FOR ATIO
to transformer leakage inductance. This spike is not indicative of actual output voltage (see Figure 4B). Delaying the enabling of the feedback amplifier allows this system to effectively ignore most or all of the voltage spike and maintain proper output voltage regulation. The enable delay time should therefore be set to the maximum expected duration of the leakage spike. This may have implications regarding output voltage regulation at minimum load (see Minimum Load Considerations). A second benefit of the enable delay time function occurs at light load. Under such conditions the amount of energy stored in the transformer is small. The flyback waveform becomes "lazy" and some time elapses before it indicates the actual secondary output voltage (see Figure 4C). So the enable delay time should also be set long enough to ignore the "irrelevant" portion of the flyback waveform at light load. Additionally, there are cases wherein the gate output is called upon to drive a large geometry MOSFET such that the turnoff transition is slowed significantly. Under such circumstances, the enable delay time may be increased to accommodate for the lengthy transition.
MOSFET GATE DRIVE
A
IDEALIZED FLYBACK WAVEFORM
B
FLYBACK WAVEFORM WITH LARGE LEAKAGE SPIKE AT HEAVY LOAD ENABLE DELAY TIME NEEDED
DISCONTINUOUS MODE RINGING "SLOW" FLYBACK WAVEFORM AT LIGHT LOAD
C
ENABLE DELAY TIME NEEDED
Figure 4
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Minimum Enable Time This function sets a minimum duration for the expected flyback pulse. Its primary purpose is to provide a minimum source current at the VC node to avoid start-up problems. Average "start-up" VC current = Minimum Enable Time * ISRC Switching Frequency Minimum enable time can also have implications at light load (see Minimum Load Considerations). The temptation is to set the minimum enable time to be fairly short, as this is the least restrictive in terms of minimum load behavior. However, to provide a "reliable" minimum start-up current of say, nominally 1A, the user should set the minimum enable time at no less that 2% of the switching period (= 1/switching frequency). CURRENT SENSE RESISTOR CONSIDERATIONS The external current sense resistor allows the user to optimize the current limit behavior for the particular application under consideration. As the current sense resistor is varied from several ohms down to tens of milliohms, peak switch current goes from a fraction of an ampere to tens of amperes. Care must be taken to ensure proper circuit operation, especially with small current sense resistor values. For example, a peak switch current of 10A requires a sense resistor of 0.025. Note that the instantaneous peak power in the sense resistor is 2.5W, and it must be rated accordingly. The LT1725 has only a single sense line to this resistor. Therefore, any parasitic resistance in the ground side connection of the sense resistor will increase its apparent value. In the case of a 0.025 sense resistor, one milliohm of parasitic resistance will cause a 4% reduction in peak switch current. So resistance of printed circuit copper traces and vias cannot necessarily be ignored. An additional consideration is parasitic inductance. Inductance in series with the current sense resistor will accentuate the high frequency components of the current waveform. In particular, the gate switching spike and multimegahertz ringing at the MOSFET can be considerably
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LT1725
APPLICATIO S I FOR ATIO
amplified. If severe enough, this can cause erratic operation. For example, assume 3nH of parasitic inductance (equivalent to about 0.1 inch of wire in free space) is in series with an ideal 0.025 sense resistor. A "zero" will be formed at f = R/(2L), or 1.3MHz. Above this frequency the sense resistor will behave like an inductor. Several techniques can be used to tame this potential parasitic inductance problem. First, any resistor used for current sensing purposes must be of an inherently noninductive construction. Mounting this resistor directly above an unbroken ground plane and minimizing its ground side connection will serve to absolutely minimize parasitic inductance. In the case of low valued sense resistors, these may be implemented as a parallel combination of several resistors for the thermal considerations cited above. The parallel combination will help to lower the parasitic inductance. Finally, it may be necessary to place a "pole" between the current sense resistor and the LT1725 ISENSE pin to undo the action of the inductive zero (see Figure 5). A value of 51 is suggested for the resistor, while the capacitor is selected empirically for the particular application and layout. Using good high frequency measurement techniques, the ISENSE pin waveform may be observed directly with an oscilloscope while the capacitor value is varied.
SENSE RESISTOR ZERO AT: R f = SENSE 2LP RSENSE COMPENSATING POLE AT: 1 f= 2(51)CCOMP FOR CANCELLATION: LP CCOMP = RSENSE(51)
GATE 51 ISENSE SGND PGND CCOMP
PARASITIC INDUCTANCE
LP
1725 F05
Figure 5
SOFT-START FUNCTION The LT1725 contains an optional soft-start function that is enabled by connecting an explicit external capacitor between the SFST pin and ground. Internal circuitry prevents the control voltage at the VC pin from exceeding that on the SFST pin.
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The soft-start function is enagaged whenever VCC power is removed, or as a result of either undervoltage lockout or thermal (overtemperature) shutdown. The SFST node is then discharged to roughly a VBE above ground. (Remember that the VC pin control node switching threshold is deliberately set at a VBE plus several hundred millivolts.) When this condition is removed, a nominal 40A current acts to charge up the SFST node towards roughly 3V. So, for example, a 0.1F soft-start capacitor will place a 0.4V/ms limit on the ramp rate at the VC node. UVLO PIN FUNCTION The UVLO pin effects an undervoltage lockout function with at threshold of roughly 1.25V. An external resistor divider between the input supply and ground can then be used to achieve a user-programmable undervoltage lockout (see Figure 6a). An additional feature of this pin is that there is a change in the input bias current at this pin as a function of the state of the internal UVLO comparator. As the pin is brought above the UVLO threshold, the bias current sourced by the part increases. This positive feedback effects a hysteresis band for reliable switching action. Note that the size of the hysteresis is proportional to the Thevenin impedance of the external UVLO resistor divider network, which makes it user programmable. As a rough rule of thumb, each 4k or so of impedance generates about 1% of hysteresis. (This is based on roughly 1.25V for the threshold and 3A for the bias current shift.) Even in good quality ground plane layouts, it is common for the switching node (MOSFET drain) to couple to the UVLO pin with a stray capacitance of several thousandths of a pF. To ensure proper UVLO action, a 100pF capacitor is recommended from this pin to ground as shown in Figure 6b. This will typically reduce the coupled noise to a few millivolts. The UVLO filter capacitor should not be made much larger than a few hundred pF, however, as the hysteresis action will become too slow. In cases where further filtering is required, e.g., to attenuate high speed supply ripple, the topology in Figure 6c is recommended. Resistor R1 has been split into two equal parts. This provides a node for effecting capacitor filtering of high
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LT1725
APPLICATIO S I FOR ATIO
VIN R1 UVLO R2 C1 100pF R2
(6a) "Standard" UVLO Divider Topology
(6b) Filter Capacitor Directly On UVLO Node
Figure 6
speed supply ripple, while leaving the UVLO pin node impedance relatively unchanged at high frequency. INTERNAL WIDE HYSTERESIS UNDERVOLTAGE LOCKOUT The LT1725 is designed to implement isolated DC/DC converters operating from input voltages of typically 48V or more. The standard operating topology utilizes a third transformer winding on the primary side that provides both feedback information and local power for the LT1725 via its VCC pin. However, this arrangement is not inherently self-starting. Start-up is effected by the use of an external "trickle-charge" resistor and the presence of an internal wide hysteresis undervoltage lockout circuit that monitors VCC pin voltage (see Figure 7). Operation is as follows: "Trickle charge" resistor R1 is connected to VIN and supplies a small current, typically on the order of a single mA, to charge C1. At first, the LT1725 is off and draws only its start-up current. After some time, the voltage on C1 (VCC) reaches the VCC turn-on threshold. The LT1725 then turns on abruptly and draws its normal supply current. Switching action commences at the GATE pin and the MOSFET begins to deliver power. The voltage on C1 begins to decline as the LT1725 draws its normal supply current, which greatly exceeds that delivered by R1. After some time, typically tens of milliseconds, the output voltage approaches its desired value. By this time, the third transformer winding is providing virtually all the supply current required by the LT1725. One potential design pitfall is undersizing the value of capacitor C1. In this case, the normal supply current
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VIN R1/2 VIN R1 UVLO C1 100pF R2
1725 F06
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C2
R1/2 UVLO
(6c) Recommended Topology to Filter High Frequency Ripple
VIN R1 VIN
+
C1 VCC
IVCC
LT1725 PGND
GATE
SGND
1725 F07
VON THRESHOLD VVCC IVCC 0 VGATE
Figure 7
drawn by the LT1725 will discharge C1 too rapidly; before the third winding drive becomes effective, the VCC turn-off threshold will be reached. The LT1725 turns off, and the VCC node begins to charge via R1 back up to the turn-on threshold. Depending upon the particular situation, this may result in either several on-off cycles before proper operation is reached, or, permanent relaxation oscillation at the VCC node. Component selection is as follows: Resistor R1 should be selected to yield a worst-case minimum charging current greater than the maximum rated LT1725 start-up current, and a worst-case maximum charging current less than the minimum rated LT1725 supply current.
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APPLICATIO S I FOR ATIO
Capacitor C1 should then be made large enough to avoid the relaxation oscillatory behavior described above. This is complicated to determine theoretically as it depends on the particulars of the secondary circuit and load behavior. Empirical testing is recommended. (Use of the optional soft-start function will lengthen the power-up timing and require a correspondingly larger value for C1.) A further note--certain users may wish to utilize the general functionality of the LT1725, but may have an available input voltage significantly lower than, say, 48V. If this input voltage is within the allowable VCC range, i.e., perhaps 20V maximum, the internal wide hysteresis range UVLO function becomes counterproductive. In such cases it is simply better to operate the LT1725 directly from the available DC input supply. The LT1737 is identical to the LT1725, with the exception that it lacks the internal wide hysteresis UVLO function. It is therefore designed to operate directly from DC input supplies in the range of 4.5V to 20V. See the LT1737 data sheet for further information. FREQUENCY COMPENSATION Loop frequency compensation is performed by connecting a capacitor from the output of the error amplifier (VC pin) to ground. An additional series resistor, often required in traditional current mode switcher controllers, is usually not required and can even prove detrimental. The phase margin improvement traditionally offered by this extra resistor will usually be already accomplished by the nonzero secondary circuit impedance, which adds a "zero" to the loop response. In further contrast to traditional current mode switchers, VC pin ripple is generally not an issue with the LT1725. The dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the VC voltage changes during the flyback pulse, but is then "held" during the subsequent "switch on" portion of the next cycle. This action naturally holds the VC voltage stable during the current comparator sense action (current mode switching).
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OUTPUT VOLTAGE ERROR SOURCES Conventional nonisolated switching power supply ICs typically have only two substantial sources of output voltage error: the internal or external resistor divider network that connects to VOUT and the internal IC reference. The LT1725, which senses the output voltage in both a dynamic and an isolated manner, exhibits additional potential error sources to contend with. Some of these errors are proportional to output voltage, others are fixed in an absolute millivolt sense. Here is a list of possible error sources and their effective contribution. Internal Voltage Reference The internal bandgap voltage reference is, of course, imperfect. Its error, both at 25C and over temperature is already included in the specifications. User Programming Resistors Output voltage is controlled by the user-supplied feedback resistor divider ratio. To the extent that the resistor ratio differs from the ideal value, the output voltage will be proportionally affected. Highest accuracy systems will demand 1% components. Schottky Diode Drop The LT1725 senses the output voltage from the transformer primary side during the flyback portion of the cycle. This sensed voltage therefore includes the forward drop, VF, of the rectifier (usually a Schottky diode). The nominal VF of this diode should therefore be included in feedback resistor divider calculations. Lot to lot and ambient temperature variations will show up as output voltage shift/ drift. Secondary Leakage Inductance Leakage inductance on the transformer secondary reduces the effective secondary-to-third winding turns ratio (NS/NT) from its ideal value. This will increase the output voltage target by a similar percentage. To the extent that secondary leakage inductance is constant from part to part, this can be accommodated by adjusting the feedback resistor ratio.
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LT1725
APPLICATIO S I FOR ATIO
Output Impedance Error An additional error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier, transformer secondary and output capacitor. Because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the "DC" lumped secondary impedance times the inverse of the off duty cycle. If the output load current remains relatively constant, or, in less critical applications, the error may be judged acceptable and the feedback resistor divider ratio adjusted for nominal expected error. In more demanding applications, output impedance error may be minimized by the use of the load compensation function (see Load Compensation). MINIMUM LOAD CONSIDERATIONS The LT1725 generally provides better low load performance than previous generation switcher/controllers utilizing indirect output voltage sensing techniques. Specifically, it contains circuitry to detect flyback pulse "collapse," thereby supporting operation well into discontinuous mode. Nevertheless, there still remain constraints to ultimate low load operation. These relate to the minimum switch on time and the minimum enable time. Discontinuous mode operation will be assumed in the following theoretical derivations. As outlined in the Operation section, the LT1725 utilizes a minimum output switch on time, tON. This value can be combined with expected VIN and switching frequency to yield an expression for minimum delivered power. 1 f 2 Minimum Power = ( VIN * tON ) 2 LPRI = VOUT * IOUT This expression then yields a minimum output current constraint:
f 1 IOUT(MIN) = VIN * tON 2 LPRI * VOUT
(
)
2
where
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f = switching frequency LPRI = transformer primary side inductance VIN = input voltage VOUT = output voltage tON = output switch minimum on time An additional constraint has to do with the minimum enable time. The LT1725 derives its output voltage information from the flyback pulse. If the internal minimum enable time pulse extends beyond the flyback pulse, loss of regulation will occur. The onset of this condition can be determined by setting the width of the flyback pulse equal to the sum of the flyback enable delay, tED, plus the minimum enable time, tEN. Minimum power delivered to the load is then: 1 f Minimum Power = VOUT * tEN + tED 2 LSEC = VOUT * IOUT
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[
(
)]
2
Which yields a minimum output constraint:
1 f * VOUT IOUT(MIN) = tED + tEN 2 LSEC
(
)
2
where
f = switching frequency LSEC = transformer secondary side inductance VOUT = output voltage tED = enable delay time tEN = minimum enable time Note that generally, depending on the particulars of input and output voltages and transformer inductance, one of the above constraints will prove more restrictive. In other words, the minimum load current in a particular application will be either "output switch minimum on time" constrained, or "minimum flyback pulse time" constrained. (A final note--LPRI and LSEC refer to transformer inductance as seen from the primary or secondary side respectively. This general treatment allows these expressions to be used when the transformer turns ratio is nonunity.)
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LT1725
APPLICATIO S I FOR ATIO
MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS The LT1725 is a current mode controller. It uses the VC node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. The internal clamp on the VC node, nominally 2.5V, then acts as an output switch peak current limit. This 2.5V at the VC pin corresponds to a value of 250mV at the ISENSE pin, when the (ON) switch duty cycle is less than 40%. For a duty cycle above 40%, the internal slope compensation mechanism lowers the effective ISENSE voltage limit. For example, at a duty cycle of 80%, the nominal ISENSE voltage limit is 220mV. This action becomes the switch current limit specification. Maximum available output power is then determined by the switch current limit, which is somewhat duty cycle dependent due to internal slope compensation action. Overcurrent conditions are handled by the same mechanism. The output switch turns on, the peak current is quickly reached and the switch is turned off. Because the output switch is only on for a small fraction of the available period, power dissipation is controlled. Loss of current limit is possible under certain conditions. Remember that the LT1725 normally exhibits a minimum switch on time, irrespective of current trip point. If the duty cycle exhibited by this minimum on time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current will not be controlled at the nominal value, and will cycle-by-cycle ratchet up to some higher level. Expressed mathematically, the requirement to maintain short-circuit control is:
tON * f <
(VF + ISC * RSEC ) where
VIN * NSP
tON = output switch minimum on time f = switching frequency ISC = short-circuit output current VF = output diode forward voltage at ISC RSEC = resistance of transformer secondary
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VIN = input voltage NSP = secondary-to-primary turns ratio ( NSEC /NPRI) Trouble is typically only encountered in applications with a relatively high product of input voltage times secondaryto-primary turns ratio and/or a relatively long minimum switch on time. (Additionally, several real world effects such as transformer leakage inductance, AC winding losses, and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate.) THERMAL CONSIDERATIONS Care should be taken to ensure that the worst-case input voltage condition does not cause excessive die temperatures. The 16-lead SO package is rated at 100C/W, and the 16-lead GN at 110C/W. Average supply current is simply the sum of quiescent current given in the specifications section plus gate drive current. Gate drive current can be computed as: IG = f * QG where QG = total gate charge f = switching frequency (Note: Total gate charge is more complicated than CGS * VG as it is frequently dominated by Miller effect of the CGD. Furthermore, both capacitances are nonlinear in practice. Fortunately, most MOSFET data sheets provide figures and graphs which yield the total gate charge directly per operating conditions.) Nearly all gate drive power is dissipated in the IC, except for a small amount in the external gate series resistor, so total IC dissipation may be computed as: PD(TOTAL) = VCC (IQ + * f * QG ), where IQ = quiescent current (from specifications) QG = total gate charge f = switching frequency VCC = LT1725 supply voltage
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APPLICATIO S I FOR ATIO
SWITCH NODE CONSIDERATIONS For maximum efficiency, gate drive rise and fall times are made as short as practical. To prevent radiation and high frequency resonance problems, proper layout of the components connected to the IC is essential, especially the power paths (primary and secondary). B field (magnetic) radiation is minimized by keeping MOSFET leads, output diode, and output bypass capacitor leads as short as possible. E field radiation is kept low by minimizing the length and area of all similar traces. A ground plane should always be used under the switcher circuitry to prevent interplane coupling. The high speed switching current paths are shown schematically in Figure 8. Minimum lead length in these paths are essential to ensure clean switching and minimal EMI. The path containing the input capacitor, transformer primary and MOSFET, and the path containing the transformer secondary, output diode and output capacitor contain "nanosecond" rise and fall times. Keep these paths as short as possible.
VCC
+
VCC
PGND
Figure 8. High Speed Current Switching Paths
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GATE DRIVE RESISTOR CONSIDERATIONS The gate drive circuitry internal to the LT1725 has been designed to have as low an output impedance as practically possible--only a few ohms. A strong L/C resonance is potentially presented by the inductance of the path leading to the gate of the power MOSFET and its overall gate capacitance. For this reason the path from the GATE package pin to the physical MOSFET gate should be kept as short as possible, and good layout/ground plane practice used to minimize the parasitic inductance. An explicit series gate drive resistor may be useful in some applications to damp out this potential L/C resonance (typically tens of MHz). A minimum value of perhaps several ohms is suggested, and higher values (typically a few tens of ohms) will offer increased damping. However, as this resistor value becomes too large, gate voltage rise time will increase to unacceptable levels, and efficiency will suffer due to the sluggish switching action.
VIN
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SECONDARY POWER PATH PRIMARY POWER PATH GATE DISCHARGE PATH
GATE
1725 F08
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TYPICAL APPLICATIO S
TELECOM 48V TO ISOLATED 15V APPLICATION The design in Figure 9 accepts an input voltage in the range of 36V to 72V and outputs an isolated 15V at up to 2A. Transformer T1 is an off-the-shelf VERSA-PAKTM #VP5-0155, produced by Coiltronics. As manufactured, it consists of six ideally identical independent windings. In this application, three windings are stacked in series on the primary side and two are placed in parallel on the secondary side. This arrangement provides a 3:1 primaryto-secondary turns ratio while maximizing overall efficiency. The remaining winding provides a primary-side ground-referred version of the flyback voltage waveform for both feedback information and providing power to the LT1725 itself. Capacitor C7 sets the switching frequency at approximately 200kHz. Optimal load compensation for the transformer and secondary circuit components is set by resistor R8. Output voltage regulation and overall efficiency are shown in the accompanying graphs. The resistor divider formed by R14 and R15 sets the undervoltage lockout threshold at about 32V, with a hysteresis band of about 2V. The soft-start and 3VOUT features are unused as shown.
VERSA-PAK is a trademark of Coiltronics, Inc
R14 820k
R3 34.0k 1%
C10 100pF
R15 33k
9 8 7 R4 3.01k 1% C6 1nF
10
3VOUT UVLO FB VC OSCAP SFST tON 6 C7 47pF 3 14 R5 51k LT1725
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T1 VP5-0155 7 D5 BAS16 6*
VIN C2 1.5F x3
D3 1N5257
3
*
D1 MBRD660 12 11 C5 1F C4 150F R13 750 1W VOUT 15V
R1 24k
R10 18 D4 1N5257
10 R11 150 4* 9 5
+
+
*1 *2
C1 22F
D2 MBRS1100 15 VCC GATE ISENSE ENDLY MENAB ROCMP 13 R6 51k 12 R7 51k 4 R8 6.2k RCMPC 5 C8 0.1F SGND PGND 11 1
C3 100pF
*
8
R12 16 5.1 2 R9 51 C9 470pF
M1 IRF620
R2 0.1
1725 F09a
Figure 9. 48V to Isolated 15V Converter
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LT1725
TYPICAL APPLICATIO S
Application Regulation
15.5 90 80 70
VOUT (V)
VIN = 48V 15.0 VIN = 36V VIN = 72V
EFFICIENCY (%)
14.5
0
0.5
1.5 1.0 ILOAD (A)
48V to Isolated 15V Application Parts List T1: Coiltronics VP5-0155 VERSA-PAK M1: International Rectifier IRF620. 200V, 0.8 N-channel MOSFET D1: Motorola MBRD660. 6A, 60V Schottky diode D2: Motorola MBRS1100. 1A, 100V Schottky diode D3, D4: 1N5257. 33V, 500mW Zener diode D5: BAS16. 75V rectifier diode C1: AVX TPSD226M025R0200. 22F, 25V tantalum capacitor C2a, C2b, C2c: Vishay/Vitramon VJ1825Y155MXB. 1.5F, 100V X7R ceramic capacitor C3: 100pF, 100V, X7R ceramic capacitor C4: Sanyo 20SV150M. 150F, 20V, OS-CON electrolytic capacitor C5: 1F, 25V, Z5U ceramic capacitor C6: 1nF, 25V, X7R ceramic capacitor C7: 47pF, 25V NPO/COG ceramic capacitor C8: 0.1F, 25V, Z5U ceramic capacitor C9: 470pF, 25V, X7R ceramic capacitor C10: 100pF, 25V, X7R ceramic capacitor R1: 24k, 1/4W, 5% resistor R2: IRC LR2010. 0.1, 1/2W current sense resistor R3: 34.0k, 1% resistor R4: 3.01k, 1% resistor R5, R6, R7: 51k, 5% resistor R8: 6.2k, 5% resistor R9: 51, 5% resistor R10: 18, 5% resistor R11: 150, 1/4W, 5% resistor R12: 5.1, 5% resistor R13a, R13b: 1.5k, 1/2W, 5% resistor R14: 820k, 5% resistor R15: 33k, 5% resistor
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Application Efficiency
VIN = 48V VOUT = 15V
60 50 40 30 20 0.01
2.0
2.5
1725 F09b
0.1 ILOAD (A)
1
10
1725 F09c
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LT1725
TYPICAL APPLICATIO S
TELECOM 48V TO ISOLATED 5V APPLICATION The design in Figure 10 accepts an input voltage in the range of 36V to 72V and outputs an isolated 5V at up to 2A. Transformer T1 is available as a Coiltronics CTX02-14989. Capacitor C7 sets the switching frequency at approximately 275kHz. Optimal load compensation for the transformer and secondary circuit components is set by resistor R8. Output voltage regulation and overall efficiency are shown in the accompanying graphs. Efficiency is shown both with and without the R11 preload. The resistor divider formed by R13 and R14 sets the undervoltage lockout threshold at about 32V, with a hysteresis band of about 2V. The soft-start and 3VOUT features are unused as shown.
T1 CTX02-14989 6 D2 BAS16 R9 18 C5 470pF
R13 820k
R3 35.7k 1%
C9 100pF
R14 33k
9 8 7 R4 3.01k 1% C6 1nF
10
3VOUT UVLO FB VC OSCAP SFST tON 6 C7 47pF 3 14 R5 51k ENDLY MENAB ROCMP 13 R6 51k 12 R7 51k 4 R8 2.7k LT1725
Application Regulation
5.25 VIN = 48V
EFFICIENCY (%)
VIN = 36V VIN = 72V 5.00
VOUT (V)
4.75
0
0.5
1.0 ILOAD (A)
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VIN
1
R10 22
R1 47k
C2 1.5F
2 R12 68
9
VOUT 5V D1 12CWQ06 R11 51 1W
11
+
C1 15F
C10 1F
C4 150pF 4
10
+
C3 150F
12
15 VCC GATE ISENSE RCMPC 5 C8 0.1F SGND PGND 11 1 16 2 M1 IRF620 R2 0.18
1725 F10a
Figure 10. 48V to Isolated 5V Converter Application Efficiency
90 80 70 60 50 40 30 20 0.01 VIN = 48V WITHOUT R11 PRELOAD
WITH R11 PRELOAD
1.5
2.0
1725 F10b
0.1 ILOAD (A)
1
10
1725 F10c
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LT1725
TYPICAL APPLICATIO S
48V to Isolated 5V Application Parts List T1: Coiltronics CTX02-14989 M1: International Rectifier IRF620. 200V, 0.8 N-channel MOSFET D1: International Rectifier 12CWQ06FN. 12A, 60V Schottky diode D2: BAS16. 75V switching diode C1: AVX TPSD156M035R0300. 15F, 35V tantalum capacitor C2: Vishay/Vitramon VJ1825Y155MXB. 1.5F, 100V, X7R ceramic capacitor C3: Sanyo 6SA150M. 150F, 6.3V, OS-CON electrolytic capacitor C4: 150pF, 100V, X7R ceramic capacitor C5: 470pF, 50V, X7R ceramic capacitor C6: 1nF, 25V X7R ceramic capacitor C7: 47pF, 25V, NPO ceramic capacitor C8: 0.1F, 25V, Z5U ceramic capacitor C9: 100pF, 25V, X7R ceramic capacitor C10: 1F, 25V, Z5U ceramic capacitor R1: 47k, 1/4W, 5% resistor R2: Panasonic type ERJ-14RSJ. 0.18, 1/4W, 5% resistor R3: 35.7k, 1% resistor R4: 3.01k, 1% resistor R5, R6, R7: 51k, 5% resistor R8: 2.7k, 5% resistor R9: 18, 5% resistor R10: 22, 5% resistor R11: 51, 1W, 5% resistor R12: 68, 5% resistor R13: 820k, 5% resistor R14: 33k, 5% resistor
U
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LT1725
PACKAGE DESCRIPTIO U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0.229 - 0.244 (5.817 - 6.198) 0.150 - 0.157** (3.810 - 3.988) 1 0.015 0.004 x 45 (0.38 0.10) 0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727) 23 4 56 7 8 0.004 - 0.0098 (0.102 - 0.249) 0.008 - 0.012 (0.203 - 0.305) 0.0250 (0.635) BSC
GN16 (SSOP) 1098
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LT1725
PACKAGE DESCRIPTIO U
S Package 16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.386 - 0.394* (9.804 - 10.008) 16 15 14 13 12 11 10 9 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988) 1 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0 - 8 TYP 0.053 - 0.069 (1.346 - 1.752) 2 3 4 5 6 7 8 0.004 - 0.010 (0.101 - 0.254) 0.014 - 0.019 (0.355 - 0.483) TYP 0.050 (1.270) BSC
S16 1098
0.016 - 0.050 (0.406 - 1.270) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT1725 RELATED PARTS
PART NUMBER LT1424-5 LT1424-9 LT1425 LT1533 LT1681/LTC1698 LT1737 DESCRIPTION Isolated Flyback Switching Regulator Isolated Flyback Switching Regulator Isolated Flyback Switching Regulator Ultralow Noise 1A Switching Regulator Isolated DC/DC Controller Chip-Set in Ouarter and Half-Brick Footprint High Power Isolated Flyback Controller COMMENTS 5V Output Voltage, No Optoisolator Required 9V Output , Regulation Maintained Under Light Loads No Third Winding or Optoisolator Required Low Switching Harmonics and Reduced EMI, VIN = 2.7V to 23V 36V VIN 72V; VOUT: 3.3V, 5V; POUT 100W; Half the cost of a DC/DC Module; Low Profile, High Efficiency Powered from a DC Supply Voltage
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 1201 2K * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2000

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